Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of CMOS devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the channel length of the CMOS devices, without excessive short-channel effects. As is known to one skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
To scale the channel lengths of CMOS devices without excessive short-channel effects, the gate oxide thickness has to be reduced, while increasing the channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 micron metal oxide semiconductor field effect transistors (MOSFETs), it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside gated ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
Although planar back-gate technology can provide improved performance through superior short-channel characteristics, such devices have either exhibited excessive parasitic capacitances leading to poor active power and speed behaviors, or have required incredibly lengthy and expensive processes which are unlikely to provide sufficient manufacturing yield.
In view of the above, there is a continued need for providing a method for fabricating a planar back-gate CMOS having low parasitic capacitance which provides good active power and speed behaviors using a methodology that is not too lengthy or costly.